1. Technical Field
The present invention relates to a semiconductor technology, and particularly to a process of fabricating a memory device and a logic device on the same chip.
2. Description of Related Art
Advanced semiconductor chips, now being manufactured in industry, are composed of logic or memory devices (e.g. DRAM devices). Logic devices are used to process information or data, while memory devices are used for data storage. In systems on which logic and memory devices are formed separately, data signals between the two may have to pass through several levels of packaging, which can result in undesirable propagation delays. For performance and cost reasons the semiconductor industry has been motivated to fabricate logic devices and memory devices on the same chip.
In a chip having DRAM devices and logic circuits thereon, the word lines of the logic circuits are preferable to have a low resistance (Rs). To gain the low resistance, a skilled person could form titanium silicide (TiSix) polycide gate, or forms tungsten/tungsten nitride (W/WNx) metal gate. These processes are not well developed and have many concerns. First, they are too complicated, thereby increasing the cycle time and lowering the yield. Second, they have metal contamination issues.
Another approach to gain the low resistance is to form a self-aligned silicide (salicide, e.g., TiSi2 or CoSi2). However, it will suffer the problem of DRAM performance, because the DRAM devices often have no heavy doped regions for salicidation.
It is an object of this invention to provide a method of fabricating a memory device and a logic device on a chip.
Other objects and advantages of this invention will become apparent to those of ordinary skill in the art having reference to the following specification in conjunction the drawings.
This present invention provides a method of fabricating a memory device and a logic device on a chip, wherein the memory device has a first gate with a first sidewall, and wherein the logic device has a second gate with a second sidewall. A substrate is provided. A first region of the substrate is provided to be used for the memory device. A second region of the substrate is provided to be used for the logic device. A first dielectric layer, a polysilicon layer, a first silicide layer, and a hard mask layer are sequentially formed over the first and the second regions of the substrate. Over the first region of the substrate, the hard mask layer, the first silicide layer, the polysilicon layer and the first dielectric layer are patterned to form the first gate. Ions are first implanted into the first region of the substrate, by using the first gate as a mask, to form a first doped region. A first spacer is formed on the first sidewall of the first gate. The substrate is partially covered by forming a second dielectric layer to cap the memory device over the first region of the substrate, and to expose the hard mask layer over the second region of the substrate. Over the second region of the substrate, the hard mask layer and the first silicide layer are removed. Over the second region of the substrate, the polysilicon layer is patterned to form the second gate. Ions are second implanted into the second region of the substrate, by using the second gate as a mask, to form a second doped region. A second spacer is formed on the second sidewall of the second gate. Ions are third implanted into the second region of the substrate, by using the second spacer and the second gate as a mask, to form a third doped region deeper than the second doped region. A second suicide layer is grown on the second gate and on the third doped region.
The process of fabricating the memory device is independent from the process of fabricating the logic devices. Moreover, the second spacer can be made of a material different from that of the first spacer. Furthermore, the second spacer may has a thickness different from that of the first spacer. These can be achieved because the first spacer is capped with the second dielectric layer when the second spacer is formed.